Semiconductor memories have been widely used in various applications for storing data. As the applications become more demanding, the systems on which the applications run require higher memory densities. Thanks to the semiconductor industry, the integration of semiconductor devices has continuously improved. Increased memory densities have increased the capacity of a single memory device from several KB to over one GB. Access time to memory devices has also challenged engineers. From time to time, different approaches to improve the access time to a memory device have been developed by brilliant engineers. One approach to improved access time is reduced signal line delay, as signal lines often cross a large group of memory cells. This approach should include refining the arrangement of a memory array and its peripheral circuitry.
FIG. 1 is a simplified view of a typical memory chip. A memory chip 100 includes several memory cell arrays 102, data input lines 104 and data output lines 106, address lines 108 and signal control lines 110. The address lines 108 include word lines and bit lines (not shown) for addressing a memory cell in the memory cell array. The signal control lines 110 are employed to transmit control signals while data reading and writing, and address lines enabling.
FIG. 2 further illustrates one conventional decoder arrangement of one of the memory cell arrays in FIG. 1. The memory array in this embodiment includes 64M memory cells 210 arranged in an array of 8K rows by 8K columns. A row decoder 202 and column decoder 204 are respectively arranged peripheral to the memory cell array 200. Together, the row decoder 202 and column decoder 204 enable some word lines 206 and bit lines 208 for addressing one or more particular memory cells 210, and accessing the data stored in the memory cells 210. As the row decoder 202 enables the word lines 206 and the column decoder 204 enables the bit lines 208, there is always a delay in accessing memory cells on the same word line. The word line length thus limits the access speed of a memory cell.
FIG. 3 illustrates an improved arrangement of the array 200, shown in FIG. 2, and its peripheral. This embodiment includes three row decoders 302a, 302b and 302c that are disposed within the memory cell array 300 and one column decoder 304 that is arranged peripheral to the memory cell. The memory cell array 300, for example, also includes 64M memory cells 310 but is divided into 4 sub-arrays, 300a–300d, such that each sub-array has 16M memory cells. As a word line in this configuration runs across a sub-array having only 2k memory cells, its length is greatly shortened. Shorter word lines to access a memory cell within a sub-array should be faster. Furthermore, row decoders positioned within the memory array can enable either the right-side or the left-side word lines, thereby improving the data access selecting rate and improving the access speed. In this arrangement, memory cell access speed is about 16 times faster than in array 200 of FIG. 2.
However, the arrangement of three row decoders within the memory cell array layout increases the layout size. The memory cell count on a memory chip decreases, which decreases the integration.
Consequently, comparing the two different decoder arrangements described above, array 200 wins the benefit of high integration layout density but fails to provide high access speed. The array 200 arrangement is limited to ROM, RAM, EPROM (Erasable Programmable ROM), EEPROM or Flash Memory, for example. Array 300 wins the benefit of high access speed but fails the high integration layout density. The array 300 arrangement is used for a higher speed register, for example.